Fixture and method for uniform electroless metal deposition on integrated circuit bond pads

ABSTRACT

A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

FIELD OF THE INVENTION

[0001] The present invention is related in general to the field ofsemiconductor devices and processes and more specifically to a fixtureand process for electroless plating bondable metal caps onto bond padsof integrated circuits having copper interconnecting metallization.

DESCRIPTION OF THE RELATED ART

[0002] In integrated circuits (IC) technology, pure or doped aluminumhas been the metallization of choice for interconnection and bond padsfor more than four decades. Main advantages of aluminum include ease ofdeposition and patterning. Further, the technology of bonding wires madeof gold, copper, or aluminum to the aluminum bond pads has beendeveloped to a high level of automation, miniaturization, andreliability. Examples of the high technical standard of wire bonding toaluminum can be found in U.S. Pat. No. 5,455,195, issued on Oct. 3, 1995(Ramsey et al., “Method for Obtaining Metallurgical Stability inIntegrated Circuit Conductive Bonds”); U.S. Pat. No. 5,244,140, issuedon Sep. 14, 1993 (Ramsey et al., “Ultrasonic Bonding Process Beyond 125kHz”); U.S. Pat. No. 5,201,454, issued on Apr. 13, 1993 (Alfaro et al.,“Process for Enhanced Intermetallic Growth in IC Interconnections”); andU.S. Pat. No. 5,023,697, issued on Jun. 11, 1991 (Tsumura,“Semiconductor Device with Copper Wire Ball Bonding”).

[0003] In the continuing trend to miniaturize the ICs, the RC timeconstant of the interconnection between active circuit elementsincreasingly dominates the achievable IC speed-power product.Consequently, the relatively high resistivity of the interconnectingaluminum now appears inferior to the lower resistivity of metals such ascopper. Further, the pronounced sensitivity of aluminum toelectromigration is becoming a serious obstacle. Consequently, there isnow a strong drive in the semiconductor industry to employ copper as thepreferred interconnecting metal, based on its higher electricalconductivity and lower electromigration sensitivity. From the standpointof the mature aluminum interconnection technology, however, this shiftto copper is a significant technological challenge.

[0004] Copper has to be shielded from diffusing into the silicon basematerial of the ICs in order to protect the circuits from the carrierlifetime killing characteristic of copper atoms positioned in thesilicon lattice. For bond pads made of copper, the formation of thincopper (I) oxide films during the manufacturing process flow has to beprevented, since these films severely inhibit reliable attachment ofbonding wires, especially for conventional gold-wire ball bonding. Incontrast to aluminum oxide films overlying metallic aluminum, copperoxide films overlying metallic copper cannot easily be broken by acombination of thermocompression and ultrasonic energy applied in thebonding process. As further difficulty, bare copper bond pads aresusceptible to corrosion.

[0005] In order to overcome these problems, a process has been disclosedto cap the clean copper bond pad with a layer of aluminum and thusre-construct the traditional situation of an aluminum pad to be bondedby conventional gold-wire ball bonding. A suitable bonding process isdescribed in U.S. Pat. No. 5,785,236, issued on Jul. 28, 1998 (Cheung etal., “Advanced Copper Interconnect System that is Compatible withExisting IC Wire Bonding Technology”). The described approach, however,has several shortcomings.

[0006] First, the fabrication cost of the aluminum cap is higher thandesired, since the process requires additional steps for depositingmetal, patterning, etching, and cleaning. Second, the cap must be thickenough to prevent copper from diffusing through the cap metal andpossibly poisoning the IC transistors. Third, the aluminum used for thecap is soft and thus gets severely damaged by the markings of themultiprobe contacts in electrical testing. This damage, in turn, becomesso dominant in the ever decreasing size of the bond pads that thesubsequent ball bond attachment is no longer reliable.

[0007] A low-cost structure and method for capping the copper bond padsof copper-metallized ICs has been disclosed on U.S. patent applicationSer. No. 60/183,405, filed on Feb. 18, 2000. The present invention isrelated to that application. The structure provides a metal layer platedonto the copper, which impedes the up-diffusion of copper. Of severalpossibilities, nickel is a preferred choice. This layer is topped by abondable metal layer, which also impedes the up-diffusion of the barriermetal. Of several possibilities, gold is a preferred choice.Metallurgical connections can then be performed by conventional wirebonding.

[0008] It is difficult, though, to plate these bond pad caps uniformlyin electroless deposition systems, because electroless deposition isaffected by local reactant concentrations and by the agitationvelocities of the aqueous solution. Deposition depletes the reactants inareas around the bond pads. Increasing the agitation of the solutiononly exacerbates the deposition non-uniformity, which is influenced bythe flow direction of the solution. The problem is further complicatedwhen a whole batch of wafers is to be plated simultaneously in order toreduce cost, since known control methods have been applied only toprocess single wafers under applied electrical bias. See, for example,U.S. Pat. No. 5,024,746, issued Jun. 18, 1991, and U.S. Pat No.4,931,149, issued Jun. 5, 1990 (Stierman et al., “Fixture and a Methodfor Plating Contact Bumps for Integrated Circuits”).

[0009] An urgent need has arisen for a reliable method of plating metalcaps over copper bond pads which combines minimum fabrication cost withmaximum plating control of all layers to be deposited. The platingmethod should be flexible enough to be applied for different IC productfamilies and a wide spectrum of design and process variations.Preferably, these innovations should be accomplished while shorteningproduction cycle time and increasing throughput, and without the need ofexpensive additional manufacturing equipment.

SUMMARY OF THE INVENTION

[0010] The present invention discloses a method and an apparatus foruniform electroless plating of layers onto exposed metallizations inintegrated circuits such as bond pads. The apparatus provides means forholding a plurality of wafers, and rotating each wafer at constant speedand synchronous within the plurality. Immersed in a plating solutionflowing in substantially laminar motion and at constant speed, themethod creates periodic superposition relative of directions and speedsof the motion of the wafers and the motion of the plating solution. Theinvention creates periodically changing wafer portions where thedirections and speeds are additive and where the directions and speedsare opposed and subtractive. Consequently, highly uniformly layers areelectrolessly plated onto the exposed metallizations of bond pads. Ifthe plated layers are bondable metals, the process transforms otherwiseunbondable bond pad metallization into bondable pads.

[0011] The present invention is related to high density and high speedICs with copper interconnecting metallization, especially those havinghigh numbers of copper metallized inputs/outputs, or “bond pads”. Thesecircuits can be found in many device families such as processors,digital and analog devices, logic devices, high frequency and high powerdevices, and in both large and small area chip categories.

[0012] It is an aspect of the present invention to be applicable to bondpad area reduction and thus to be in support of the shrinking of ICchips. Consequently, the invention helps to alleviate the spaceconstraint of continually shrinking applications such as cellularcommunication, pagers, hard disk drives, laptop computers and medicalinstrumentation.

[0013] Another aspect of the invention is to deposit the bond pad metalcaps by the self-defining process of electroless plating, thus avoidingcostly photolithographic and alignment techniques.

[0014] Another aspect of the invention is to accomplish the control andstability needed for successful electroless metal deposition.

[0015] Another aspect of the invention is to advance the process andreliability of wafer-level multi-probing by eliminating probe marks andsubsequent bonding difficulties.

[0016] Another object of the invention is to provide design and processconcepts which are flexible so that they can be applied to many familiesof semiconductor products, and are general so that they can be appliedto several generations of products.

[0017] Another object of the invention is to use only designs andprocesses most commonly employed and accepted in the fabrication of ICdevices, thus avoiding the cost of new capital investment and using theinstalled fabrication equipment base.

[0018] These objects have been achieved by the teachings of theinvention concerning selection criteria, process flows and controlssuitable for mass production. Various modifications have beensuccessfully employed to satisfy the requirements of different platingsolutions.

[0019] In the first embodiment of the invention, an apparatus isdisclosed for uniform electroless plating of layers onto exposedmetallizations in integrated circuits, such as bond pads, which arepositioned on the active surface of semiconductor wafers. The apparatusis suitable for simultaneous processing of a plurality of wafers. Itprovides rotation at constant speed synchronously to the wafers and thuscreates relative motion, between the wafers and the chemical solution ofa plating bath.

[0020] In the second embodiment of the invention, a plating apparatus isdisclosed which combines the rotation of the wafers with the laminarmotion at constant speed of the plating solution. The superposition ofrotational and laminar motions and the resulting periodic changes ofdirection and speed create periodically changing wafer portions wherethe speeds are additive and where the speeds are subtractive. Theresulting controlled electroless deposition of metal creates uniformlyplated layers.

[0021] In all preferred embodiments, the various metal layers aredeposited by electroless plating, thus avoiding the need for expensivephotolithographic definition steps.

[0022] The technical advances represented by the invention, as well asthe aspects thereof, will become apparent from the following descriptionof the preferred embodiments of the invention, when considered inconjunction with the accompanying drawings and the novel features setforth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a schematic side view of the first embodiment of theinvention, the apparatus for controlled electroless plating including aplurality of integrated circuit wafers.

[0024]FIG. 2 is a schematic end view of the first embodiment of theinvention, the apparatus for controlled electroless plating.

[0025]FIG. 3 is a schematic composite side view and cross section of thesecond embodiment of the invention, the plating tank and apparatus forcontrolled electroless plating.

[0026]FIG. 4 is a schematic composite end view and cross section of thesecond embodiment of the invention, the plating tank and apparatus forcontrolled electroless plating.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Illustrating the first embodiment of the invention, generallydesignated 100, FIG. 1 shows a side view of the apparatus for controlledelectroless plating of uniform metal layers onto exposed metallizationson a plurality of integrated circuit (IC) wafers 101. Usually, there are10 to 30 wafers in a batch. In the fixture 100, the wafers 101 are heldapproximately parallel to each other at predetermined distances 102. Atypical distance is in the range from about 5 to 10 mm and thus severaltimes wider than the thickness of a wafer (about 0.25 to 0.75 mm). Attheir rims, the wafers are loosely held in grooves 103 of rollers. InFIG. 1, two rollers are shown, the bottom roller 105 and the captureroller 104. The rollers are made of chemically inert plastic materialsuch as polypropylene. Instead of grooved rollers, toothed rollers maybe used. A practical groove is about 2 to 5 mm deep. In the preferredembodiments, there are three rollers (see FIG. 2) employed to containthe wafers.

[0028] It is an essential feature of the invention that the rollers canbe set in rotational motion by their respective driven gears 104 a and105 a, which are driven by a central sun gear 110 (partially obscured inFIG. 1, but fully visible in FIG. 2). With this feature, the turning sungear 110 drives all rollers at the same speed. Consequently, all wafers101, contained in the roller grooves 103 and held in secure contact withthe roller material by their weight, are rotating in unison at constantspeed and in synchronous manner. For wafers of 200 mm diameter,preferred rotation speeds are in the range of about 0.5 to 5 rpm.

[0029] In FIG. 2, fixture 100 is displayed in a schematic end view. Allthree rollers are indicated by their respective driven gears 104 a, 105a and 106 a. The position of a 200 mm IC wafer is indicated by dashedline 101 a. For practical ease of loading and unloading of the wafers,one of the rollers (in FIGS. 1 and 2, the capture roller 104) has ahandle 104 b fixed to a pivot arm 201 so that the roller 104 can beswung sidewise manually. In FIG. 2, the closed position is indicated bysolid lines for pivot arm 201 and driven gear 104 b, the opened positionby dashed lines.

[0030] Illustrating the second embodiment of the invention, generallydesignated 300, as well as the process for electroless plating, FIGS. 3and 4 show schematically the cross section through a plating tank filledby the liquid plating solution 302 up to the surface 302 a of thesolution. The plating tank has an outer wall 301 a and an inner wall 301b, separated by a gap 303, which enables the reflow of the liquid. InFIGS. 3 and 4, arrows indicate the flow of the liquid solution. As canbe seen, the solution enters the tank from the bottom (arrows 310),moves in laminar flow at constant speed upward (for example, at a speedof 20 cm/min) through the tank, and exits from the tank surface (arrows311) by overflowing into the reflow gap 303. After reaching the tankbottom, the flow cycle begins anew.

[0031] Further shown in FIGS. 3 and 4 is the apparatus/fixture forholding a plurality of wafers, explained in FIG. 1 and 2. In FIG. 3, thefixture is illustrated in side view 320 as in FIG. 1; in FIG. 4, thefixture is illustrated in end view 420 as in FIG. 2. As can be seen fromFIG. 3, the fixture is loaded with a batch of wafers 321, contained ontheir side edges while their active and passive surfaces covered by aprotective resist are exposed to the plating solution (the passivesurfaces are covered by a protective resist).

[0032] On its laminar flow from the bottom to the surface of the tank,the plating solution flows substantially parallel to the active surfacesof the wafers contained in the fixture. In order to control theelectroless plating process and achieve uniform metal layer deposition,it is an essential feature of the present invention that the directionand speed of the laminarly moving solution is superposed by anotherrelative motion. This additional relative motion is generated by therotation at constant speed of the wafers held in the fixture (thefixture causes the wafers to move synchronously with each other). Withthis additional motion, a periodic superposition of directions andspeeds is achieved between the motion of the wafers and the motion ofthe solution, resulting in periodically changing wafer portions wherethe directions and speeds are additive and where the directions andspeeds are opposed and subtractive.

[0033] This periodic relative motion in changing directions between theplating solution and the rotating wafers is crucial for creatinguniformly plated layers on exposed metallizations of the active wafersurfaces by controlled electroless deposition.

[0034] The preferred electroless process flow used for plating uniformmetal layers as caps onto exposed copper metallizations such as bondpads of ICs positioned on the active surface of semiconductor wafers hasthe following steps. The example is chosen for fabricating a capconsisting of two metal layers.

[0035] Step 1: Coating the passive surface of the IC wafers with resistusing a spin-on technique. This coat will prevent accidental metaldeposition on the passive surface of the wafers.

[0036] Step 2: Baking the resist, typically at 110° C. for a time periodof about 30 toe 60 minutes.

[0037] Step 3: Cleaning of the exposed bond pad copper surface using aplasma ashing process for about 2 minutes.

[0038] Step 4: Loading the wafers into the apparatus/fixture describedabove for controlled electroless plating.

[0039] Step 5: Cleaning by immersing the wafers, having the exposedcopper of the bond pads, in a solution of sulfuric acid, nitric acid, orany other acid, for about 50 to 60 seconds.

[0040] Step 6: Rinsing in overflow rinser for about 100 to 180 seconds.

[0041] Step 7: Immersing the wafers in a catalytic metal chloridesolution, such as palladium chloride, for about 40 to 80 seconds. Thisstep “activates” the copper surface, i.e., a layer of seed metal (suchas palladium) is deposited onto the clean non-oxidized copper surface.

[0042] Step 8: Rinsing in dump rinser for about 100 to 180 seconds.

[0043] Step 9: Initiating laminar motion at constant speed of firstelectroless plating solution in plating tank. If nickel is to be plated,the solution consists of an aqueous solution of a nickel salt, such asnickel chloride, sodium hypo-phosphite, buffers, complexors,accelerators, stabilizers moderators, and wetting agents.

[0044] Step 10: Immersing the wafers into the electroless platingsolution. The solution, flowing in laminar motion at constant speed,flows substantially parallel to the active surface of the wafers.

[0045] Step 11: Initiating rotation of wafers at constant speed andsynchronously with each other, initiating superposition of directionsand speeds of the waver motion and the solution motion.

[0046] Step 12: Plating layer electrolessly. If a nickel layer is to beplated, plating between 150 and 180 seconds will deposit about 0.4 to0.6 μm thick nickel layer.

[0047] Step 13: Stopping rotation of wafers.

[0048] Step 14: Removing wafers from plating solution.

[0049] Step 15: Rinsing in dump rinser for about 100 to 180 seconds.

[0050] Step 16: Repeating Steps 9 through 15 for second electrolessplating solution, varying composition of solution and plating timeaccording to metal-to-be-plated.

[0051] Step 17: Repeating Steps 9 through 15 for third electrolessplating solution, varying composition of solution and plating timeaccording to metal-to-be-plated.

[0052] Step 18: Stripping wafer protection resist from passive surfaceof wafers for about 8 to 12 minutes.

[0053] Step 19: Spin rinsing and drying for about 6 to 8 minutes.

[0054] While this invention has been described in reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiments, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. As an example, the invention can be applied to ICbond pad metallizations other than copper, which are difficult orimpossible to bond by conventional ball or wedge bonding techniques,such as alloys of refractory metals and noble metals. As anotherexample, the invention applies to immersion plating and autocatalyticplating. A sequence of these plating techniques is particularly usefulfor electroless plating of gold layers. As another example, theinvention provides for easy control of the uniformity of plated layersby modifying individually the flow speed of the plating solution or therotation speed of the wafers, even in the course of one platingdeposition. It is therefore intended that the appended claims encompassany such modifications or embodiments.

We claim:
 1. A method for controlled electroless plating of uniformmetal layers onto exposed metallizations in integrated circuitspositioned on the active surface of semiconductor wafers, comprising thesteps of: maintaining a plurality of said wafers approximately parallelto each other at predetermined distances; immersing said wafers into anelectroless plating solution flowing in laminar motion at constant speedsubstantially parallel to said active surface of said wafers; rotatingeach of said wafers at constant speed and synchronously with each other;and creating periodic relative motion in changing directions betweensaid plating solution and said wafers, thereby uniformly plating layersonto said exposed metallizations by controlled electroless deposition.2. The method according to claim 1 wherein said exposed metallizationsare non-oxidized copper metallizations of bond pads positioned in saidintegrated circuits having copper metallizations.
 3. The methodaccording to claim 1 wherein said plurality of said wafers comprisesbetween 10 and 30 wafers.
 4. The method according to claim 1 whereinsaid relative motion comprises a periodic superposition of directionsand speeds of the motion of said wafers and the motion of said solution,thus creating periodically changing wafer portions where the directionsand speeds are additive and where the directions and speeds are opposedand subtractive.
 5. The method according to claim 1 further comprisingthe steps of: inserting the wafers into a clean-up or presoak bath;removing the wafers from the clean-up or presoak bath; and inserting thewafers into the plating solution.
 6. An apparatus for controlledelectroless plating of uniform layers onto exposed metallizations inintegrated circuits positioned on the active surface of semiconductorwafers, comprising: means for holding a plurality of said wafersapproximately parallel to each other at predetermined distances; meansfor rotating each wafer of said plurality; means for electroless platingin a solution flowing substantially in laminar motion at constant speedsubstantially parallel to said active surface of said wafers; and meansfor creating periodic relative motion in changing directions betweensaid plating solution and said wafers, whereby uniformly plated layersare electrolessly deposited onto said exposed metallizations.
 7. Theapparatus according to claim 6 wherein said means for rotating waferscreates constant wafer speed and synchronous rotation between wafers. 8.The apparatus according to claim 6 wherein said holding means comprisesa plurality of grooved rollers positioned parallel to each other, eachof said rollers having grooves around said rollers, shaped to supportsaid wafers, the respective grooves of each roller positioned in a planesuitable for holding one of said wafers.
 9. The apparatus according toclaim 8 wherein said plurality of rollers comprises three rollers. 10.The apparatus according to claim 6 wherein said rotating means comprisesa central sun gear driving said grooved rollers positioned in parallelaround said central gear.
 11. The apparatus according to claim 6 furtherincluding a motor associated with the apparatus which rotates theapparatus in a plating solution.